Statistical static timing analysis
Open-knowledge reference entry
Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits since the 1960s. However the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. This has led to considerable research into statistical static timing analysis, which replaces the normal deterministic timing of gates and interconnects with probability distributions, and gives a distribution of possible circuit outcomes rather than a single outcome.
Comparison with conventional STA
Deterministic STA is popular for good reasons:
It requires no vectors, so it does not miss paths.
The run time is linear in circuit size (for the basic algorithm).
The result is conservative.
It typically uses some fairly simple libraries (typically delay and output slope as a function of input slope and output load).
It is easy to extend to incremental operation for use in optimization.
STA, while very successful, has a number of limitations:
Cannot easily handle within-die correlation, especially if spatial correlation is included.
Needs many corners to handle all possible cases.
If there are significant random variations, then in order to be conservative at all times, it is too pessimistic to result in competitive products.
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