Interrupts in 65xx processors
Open-knowledge reference entry
The 65xx family of microprocessors, consisting of the MOS Technology 6502 and its derivatives, the WDC 65C02, WDC 65C802 and WDC 65C816, and CSG 65CE02, all handle interrupts in a similar fashion. There are three hardware interrupt signals common to all 65xx processors and one software interrupt, the BRK instruction. The WDC 65C816 adds a fourth hardware interrupt—ABORT, useful for implementing virtual memory architectures—and the COP software interrupt instruction (also present in the 65C802), intended for use in a system with a coprocessor of some type (e.g., a floating-point processor).
Interrupt types
The hardware interrupt signals are all active low, and are as follows:
RESET
a reset signal, level-triggered
NMI
a non-maskable interrupt, edge-triggered
IRQ
a maskable interrupt, level-triggered
ABORT
a special-purpose, non-maskable interrupt (65C816 only, see below), level-triggered
The detection of a RESET signal causes the processor to enter a system initialization period of six clock cycles, after which it sets the interrupt request disable flag in the status register and loads the program counter with the values stored at the processor initialization vector ($00FFFC–$00FFFD) before commencing execution. If operating in native mode, the 65C816/65C802 are switched back to emulation mode and stay there until returned to native mode under software control.
The detection of an NMI or IRQ signal, as well as the execution of a BRK instruction, will cause the same overall sequence of events, which are, in order:
The processor completes the current instruction and updates registers or memory as required before responding to the interrupt.
65C816/65C802 when operating in native mode: The program bank register (PB, the A16-A23 part of the address bus) is pushed onto the hardware stack.
The most significant byte (MSB) of the program counter (PC) is pushed onto the stack.
The least significant byte (LSB) of the program counter is pushed onto the stack.
The status register (SR) is pushed onto the stack.
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