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Ampere (microarchitecture)

GPU microarchitecture designed by NVIDIA

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Record originEnglish Wikipedia
Text licenseCC BY-SA 4.0
Source revisionSep 1, 2026
Entity authorityQ65043984 ↗
Source-derived summary

Ampere is the codename for a graphics processing unit (GPU) microarchitecture developed by Nvidia as the successor to both the Volta and Turing architectures. It was officially announced on May 14, 2020, and is named after French mathematician and physicist André-Marie Ampère.

Nvidia announced the Ampere architecture GeForce 30 series consumer GPUs at a GeForce Special Event on September 1, 2020. Nvidia announced the A100 80 GB GPU at SC20 on November 16, 2020. Mobile RTX graphics cards and the RTX 3060 based on the Ampere architecture were revealed on January 12, 2021.

Nvidia announced Ampere's successor, Hopper, at GTC 2022, and "Ampere Next Next" (Blackwell) for a 2024 release at GPU Technology Conference 2021.

Details

Architectural improvements of the Ampere architecture include the following:

CUDA Compute Capability 8.0 for A100 and 8.6 for the GeForce 30 series

TSMC's 7 nm FinFET process for A100

Custom version of Samsung's 8 nm process (8N) for the GeForce 30 series

Third-generation Tensor Cores with FP16, bfloat16, TensorFloat-32 (TF32) and FP64 support and sparsity acceleration. The individual Tensor cores have with 256 FP16 FMA operations per clock 4x processing power (GA100 only, 2x on GA10x) compared to previous Tensor Core generations; the Tensor Core Count is reduced to one per SM.

Second-generation ray tracing cores; concurrent ray tracing, shading, and compute for the GeForce 30 series

High Bandwidth Memory 2 (HBM2) on A100 40 GB & A100 80 GB

GDDR6X memory for GeForce RTX 3090, RTX 3080 Ti, RTX 3080, RTX 3070 Ti

Double FP32 cores per SM on GA10x GPUs

NVLink 3.0 with a 50 Gbit/s per pair throughput

PCI Express 4.0 with SR-IOV support (SR-IOV is reserved only for A100)

Multi-instance GPU (MIG) virtualization and spatial GPU partitioning feature in A100 supporting up to seven instances

PureVideo feature set K hardware video decoding with AV1 hardware decoding for the GeForce 30 series and feature set J for A100

5 NVDEC for A100

Adds new hardware-based 5-core JPEG decode (NVJPG) with YUV420, YUV422, YUV444, YUV400, RGBA. Should not be confused with Nvidia NVJPEG (GPU-accelerated library for JPEG encoding/decoding)

Chips

GA100

GA102

GA103

GA104

GA106

GA107

GA10B

Comparison of Compute Capability: GP100 vs GV100 vs GA100

Comparison of Precision Support Matrix

Legend:

FPnn: floating point with nn bits

INTn: integer with n bits

INT1: binary

TF32: TensorFloat32

BF16: bfloat16

Comparison of Decode Performance

Ampere dies

A100 accelerator and DGX A100

The Ampere-based A100 accelerator was announced and released on May 14, 2020. The A100 features 19.5 teraflops of FP32 performance, 6912 FP32/INT32 CUDA cores, 3456 FP64 CUDA cores, 40 GB of graphics memory, and 1.6 TB/s of graphics memory bandwidth. The A100 accelerator was initially available only in the 3rd generation of DGX server, including 8 A100s.

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“Ampere (microarchitecture)” enters the record as gPU microarchitecture designed by NVIDIA. Crown Archives preserves that source wording while asking what Ampere, microarchitecture and designed can confirm, complicate or overturn.

Editorial reviewA practical starting point whose main value is the path it opens into stronger specialist and primary sources. The current lead gives the account dated anchors—2020, 2021, 2022, 2024—that can be checked directly. The linked authority record independently contributes the date 2020-09-01. Its strongest next move is a source search built around Ampere, microarchitecture and designed.
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This entry incorporates text from “Ampere (microarchitecture)” on English Wikipedia. Contributors are listed in the page history. Text is available under the Creative Commons Attribution-ShareAlike 4.0 License. Selected authority identifiers and statements are retrieved from Wikidata under CC0; their references and qualifiers remain part of the verification path.