CACrown ArchivesThe cinema collection
Menu
Research dossier · General Reference

ARM Cortex-A15

ARM Cortex-A15 MPCore

Cross-disciplinary reference desk with index cards, atlas, dictionary and catalogue
General referenceInterpretive dossier study · Crown Archives visual atlas
Record originEnglish Wikipedia
Text licenseCC BY-SA 4.0
Source revisionAug 12, 2026
Entity authorityQ2819371
Source-derived summary

The ARM Cortex-A15 MPCore is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor with out-of-order superscalar pipeline running at up to 2.5 GHz.

Overview

ARM has claimed that the Cortex-A15 core is 40 percent more powerful than the Cortex-A9 core with the same number of cores at the same speed. The first A15 designs came out in the autumn of 2011, but products based on the chip did not reach the market until 2012.

Key features of the Cortex-A15 core are:

40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM with a 32-bit virtual address space.

15 stage integer/17–25 stage floating point pipeline, with out-of-order speculative issue 3-way superscalar execution pipeline

4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (CCI-400, an AMBA-4 coherent interconnect) and 4 clusters per chip with CCN-504. ARM provides specifications but the licensees individually design ARM chips, and AMBA-4 scales beyond 2 clusters. The theoretical limit is 16 clusters; 4 bits are used to code the CLUSTERID number in the CP15 register (bits 8 to 11).

DSP and NEON SIMD extensions onboard (per core)

VFPv4 Floating Point Unit onboard (per core)

Hardware virtualization support

Thumb-2 instruction set encoding to reduce the size of programs with little impact on performance

TrustZone security extensions

Jazelle RCT for JIT compilation

Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution

32 KB data + 32 KB instruction L1 cache per core

Integrated low-latency level-2 cache controller, up to 4 MB per cluster

Chips

First implementation came from Samsung in 2012 with the Exynos 5 Dual, which shipped in October 2012 with the Samsung Chromebook Series 3 (ARM version), followed in November by the Google Nexus 10.

Press announcements of current implementations:

Broadcom SoC

HiSilicon K3V3

Nvidia Tegra 4 (Wayne) and Tegra K1.

Editorial summary

The public source identifies “ARM Cortex-A15” as aRM Cortex-A15 MPCore. This brief keeps that definition visible, then builds a research path around Cortex-A15 and MPCore.

Editorial reviewA concise reference frame for defining the subject, testing terminology and identifying the institution closest to the evidence. The current lead gives the account dated anchors—2011, 2012—that can be checked directly. The selected authority fields contribute no independent date. Its value is orientation rather than verdict, with Cortex-A15 and MPCore providing the first useful test.
Editorial analysis

Why this record matters

A short description can identify a subject without explaining its stakes. For “ARM Cortex-A15”, the useful work is to connect “aRM Cortex-A15 MPCore” to the records capable of establishing context and consequence.

Evidence profile

The citation trail is more important than the brevity of the summary: it shows where individual claims can be examined in context. The source revision retrieved here is dated Aug 12, 2026. The linked authority identifier is Q2819371. 1 of 1 selected statements include explicit references; 0 carry qualifiers and 0 use preferred rank. The first chronological checks are 2011 and 2012.

Critical limits

The absence of detail may reflect summary conventions rather than a lack of surviving documentation. The lead is largely declarative, so disagreement and counter-evidence require a deliberate search beyond the opening account. Authority statements aid reconciliation but still require their own references, qualifiers and ranks to be checked.

How to read it

Use the entry as an orientation point, then follow its citations and revision history. Names, dates and institutional relationships should be checked against the original record.

Best used for
  • Subject orientation
  • Search vocabulary
  • Locating named sources
Verify next

The closest primary source, responsible institution and strongest cited specialist reference.

Three-step research path

  1. Establish the record: confirm the title “ARM Cortex-A15”, its source revision and the description used here.
  2. Expand the search: follow ARM Cortex-A15 primary sources, ARM Cortex-A15 archive and Cortex-A15 research across catalogues and specialist indexes.
  3. Test the account: compare the strongest cited source with the responsible institution’s current record and note any disagreement.

Questions for further research

  1. Which source most directly establishes the central claim about “ARM Cortex-A15”?
  2. Which cited source is closest to the event, object or claim?
  3. Which institution is responsible for the underlying evidence?
Subject index

Search terms from this dossier

Source & attribution

This entry incorporates text from ARM Cortex-A15” on English Wikipedia. Contributors are listed in the page history. Text is available under the Creative Commons Attribution-ShareAlike 4.0 License. Selected authority identifiers and statements are retrieved from Wikidata under CC0; their references and qualifiers remain part of the verification path.